Topic: "arty-a7"
eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Language: Tcl - Size: 36.1 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 933 - Forks: 209
hex-five/multizone-fpga Fork of sifive/freedom
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 SoC is Hex Five's official reference platform for its MultiZone Security Trusted Execution Environment and MultiZone Security Trusted Firmware. The X300 is an enhanced secure version of the - now archived - SiFive's Freedom E300 Platform built around the RISC-V Rocket chip originally developed at U.C. Berkeley.
Language: Scala - Size: 212 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 24 - Forks: 5
viktor-nikolov/MicroBlaze-DDR3-tutorial
Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
Language: C - Size: 11.4 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 15 - Forks: 2
Thraetaona/Innervator
Innervator: Hardware Acceleration for Neural Networks
Language: VHDL - Size: 2.86 MB - Last synced at: about 1 month ago - Pushed at: 10 months ago - Stars: 14 - Forks: 1
timothystotts/fpga-serial-mem-tester-3
A small FPGA and APSoC project of different implementations for testing byte-by-byte a serial flash. Refresh of fpga-serial-mem-tester-1 and -2.
Language: Tcl - Size: 24.5 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 4 - Forks: 0
Luke7412/IpLibrary
Library containing various VHDL IPs
Language: SystemVerilog - Size: 486 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 0
timothystotts/fpga-serial-acl-tester-3
A small FPGA and APSoC project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. Refresh of fpga-serial-acl-tester-1 and -2.
Language: Tcl - Size: 35 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0
rtbnb/SixteenShadesOfCpu
A 16-bit RISC CPU implemented in VHDL on an Arty A7-35T development board
Language: VHDL - Size: 258 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 2 - Forks: 0
Luke7412/IpDemonstrators
Vivado demonstrator projects for IPs in IpLibrary repo.
Language: Python - Size: 257 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
timothystotts/fpga-colors-tester-3
A small FPGA and APSoC project of multiple implementation for testing and comparing color mixing between discrete RGB LEDs and an OLED RGB display
Language: Tcl - Size: 36.3 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0
timothystotts/fpga-iic-hygro-tester-3
A small FPGA and APSoC project of different implementations for testing Temperature and Relative Humidity readings of a IIC sensor
Language: Tcl - Size: 13.4 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0
timothystotts/fpga-iic-hygro-tester-1
A small FPGA project of different implementations for testing Temperature and Relative Humidity readings of a IIC sensor
Language: VHDL - Size: 109 MB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
klimatt/arty_a7
A playground with various modules, written in SystemVerilog, with a project setup to simplify working routines.
Language: SystemVerilog - Size: 27.7 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0
riccardonicolaidis/Particle-Detector-ARTY-A7
Implementation of a particle detector using a cheap FPGA developement board. The FPGA exploits some ADCs and then if there are coincidences in the signals, the event is recorded.
Language: VHDL - Size: 25.5 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
riccardonicolaidis/PmodSD_Arty_A7_Project
In this project I wanted to implement a microprocessor on an FPGA with the ability to write files onto an SD card (micro SD in particular) exploiting the Arty A7 development board and the Digilent PModSD.
Language: VHDL - Size: 144 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 1
riccardonicolaidis/Sampler_Pmod_AD1
Implementation of a sampler using the XADC mounted on the Arty A7-35T development board and the PmodAD1 by Digilent (AD7476A).
Language: VHDL - Size: 26 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0
riccardonicolaidis/project_getting_started_Vivado_Vitis
Personal revision of the tutorial "Getting started with Vivado and Vitis for Baremetal system" by Digilent.
Language: VHDL - Size: 87.8 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0
suoglu/axi-lite-slave
Collection of some simple AXI4-Lite slaves.
Last synced at: about 2 years ago - Stars: 0 - Forks: 0