Topic: "systemrdl-compiler"
SystemRDL/systemrdl-compiler
SystemRDL 2.0 language compiler front-end
Language: C++ - Size: 2.53 MB - Last synced at: 4 days ago - Pushed at: 2 months ago - Stars: 251 - Forks: 70
Juniper/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Language: Verilog - Size: 7.08 MB - Last synced at: 8 days ago - Pushed at: 7 months ago - Stars: 199 - Forks: 71
SystemRDL/PeakRDL
Control and status register code generator toolchain
Language: Python - Size: 160 KB - Last synced at: 16 days ago - Pushed at: 21 days ago - Stars: 127 - Forks: 27
SystemRDL/PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Language: Python - Size: 904 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 64 - Forks: 46
SystemRDL/PeakRDL-html
Generate address space documentation HTML from compiled SystemRDL input
Language: JavaScript - Size: 5.56 MB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 50 - Forks: 18
SystemRDL/PeakRDL-ipxact
Import and export IP-XACT XML register models
Language: Python - Size: 144 KB - Last synced at: 15 days ago - Pushed at: 7 months ago - Stars: 34 - Forks: 13
sdnellen/open-register-design-tool Fork of Juniper/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Language: Verilog - Size: 7.16 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 15 - Forks: 3
Risto97/PeakRDL-halcpp
C++ 17 Hardware abstraction layer generator from systemrdl
Language: C++ - Size: 1.23 MB - Last synced at: 2 days ago - Pushed at: 8 months ago - Stars: 12 - Forks: 6
