gundasrikar/IC-Design-IHC-Cadence-Virtuoso-Analog-to-Digital-Circuit

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gundasrikar/IC-Design-VCO-Cadence-Virtuoso-Digital-Circuit

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KAMATHAM19/RTL-to-GDSII-ASIC-design-of-Counter

The objective is to take a simple counter design from the RTL (Register Transfer Level) stage to the GDSII format using Cadence tools with a 90nm Process Design Kit (PDK).. The tools used in this process include Xcelium for simulation and coverage analysis, Genus for synthesis, Innovus for physical design, and Pegasus/PVS for physical verification.

Language: Tcl - Size: 56.6 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0