GitHub / 0xArt / Passe_Passe_Network_Switch

A FPGA layer 2 network switch with the unique ability of having virtual ports that can transmit and receive UDP data.

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PURL: pkg:github/0xArt/Passe_Passe_Network_Switch

Stars: 6
Forks: 1
Open issues: 0

License: mit
Language: SystemVerilog
Size: 291 KB
Dependencies parsed at: Pending

Created at: over 2 years ago
Updated at: 6 months ago
Pushed at: 6 months ago
Last synced at: 6 months ago

Topics: ethernet, fpga, layer-2, network, rgmii, rmii, switch, udp

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