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GitHub / 1sand0s / SSP-Master-and-Slave-Verilog-Module

FSM based SPI/SSP Master and Slave Verilog Module

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/1sand0s%2FSSP-Master-and-Slave-Verilog-Module

Stars: 4
Forks: 2
Open issues: 0

License: None
Language: Verilog
Size: 4.88 KB
Dependencies parsed at: Pending

Created at: over 5 years ago
Updated at: 2 months ago
Pushed at: over 5 years ago
Last synced at: about 1 month ago

Topics: fifo-buffer, rtl, verilog, verilog-hdl

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