GitHub / AbhishekTaur / System-Verilog-Practice
Repository for system verilog labs from cadence
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Stars: 6
Forks: 5
Open issues: 0
License: None
Language: SystemVerilog
Size: 86.9 KB
Dependencies parsed at: Pending
Created at: over 5 years ago
Updated at: over 2 years ago
Pushed at: over 5 years ago
Last synced at: about 2 years ago
Topics: cadence, cadence-incisive, systemverilog, verilog
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