GitHub / Charmve / AccANN
🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*
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PURL: pkg:github/Charmve/AccANN
Stars: 20
Forks: 1
Open issues: 3
License: None
Language:
Size: 396 KB
Dependencies parsed at: Pending
Created at: over 4 years ago
Updated at: about 2 months ago
Pushed at: about 1 year ago
Last synced at: 3 days ago
Commit Stats
Commits: 28
Authors: 1
Mean commits per author: 28.0
Development Distribution Score: 0.0
More commit stats: https://commits.ecosyste.ms/hosts/GitHub/repositories/Charmve/AccANN
Topics: accelerator, addernet, asic, charmve, cnn, deep-learning, fpga, fpga-hardware, ghostnet, gpu-acceleration, hardware, hardware-acceleration, neurips, paper, verilog
Funding Links https://github.com/sponsors/Charmve