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GitHub / Eric-Souza / johnson-counter
An algorithm, developed in Verilog hardware design language (HDL), that implements a Johnson Counter, which counts 2n states if the number of bits is n. This system was developed as a Logical Systems subject exercise (UFMG).
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Eric-Souza%2Fjohnson-counter
Stars: 0
Forks: 0
Open Issues: 0
License: None
Language: SystemVerilog
Repo Size: 1000 Bytes
Dependencies: pending
Created: almost 3 years ago
Updated: almost 3 years ago
Last pushed: almost 3 years ago
Last synced: over 1 year ago
Topics: computer-science, hardware, hdl, logical-operators, ufmg, verilog