GitHub / JASLemos / RV32I

A 32 bit RISC-V RV32I CPU described in Verilog HDL.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JASLemos%2FRV32I
PURL: pkg:github/JASLemos/RV32I

Stars: 0
Forks: 0
Open issues: 0

License: None
Language: VHDL
Size: 14.1 MB
Dependencies parsed at: Pending

Created at: 6 months ago
Updated at: about 2 months ago
Pushed at: about 2 months ago
Last synced at: about 2 months ago

Topics: computer-architecture, fpga, verilog-hdl

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