GitHub / akifislam / Simulation-on-ModelSim-with-Verilog-HDL
This repository contains codes of Verilog which is a Hardware Definition Language. These code can be easily compiled and simulate with a software called ModelSim.
Stars: 0
Forks: 2
Open issues: 2
License: None
Language: Verilog
Size: 5.86 KB
Dependencies parsed at: Pending
Created at: over 3 years ago
Updated at: over 2 years ago
Pushed at: over 3 years ago
Last synced at: about 1 year ago
Topics: circuit-simulator, digital-electronics, verilog, verilog-hdl
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