GitHub / princeofpython / Computer-Architecture
Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.
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PURL: pkg:github/princeofpython/Computer-Architecture
Stars: 14
Forks: 5
Open issues: 1
License: None
Language: Verilog
Size: 2.67 MB
Dependencies parsed at: Pending
Created at: almost 6 years ago
Updated at: over 2 years ago
Pushed at: about 4 years ago
Last synced at: about 2 years ago
Topics: alu, cpu, pipelining, processor, risc-v, riscv32, verilog