GitHub / zslwyuan / Zynq_HLS_DDR_Dataflow_kernel_2mm
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
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PURL: pkg:github/zslwyuan/Zynq_HLS_DDR_Dataflow_kernel_2mm
Stars: 11
Forks: 2
Open issues: 0
License: None
Language: VHDL
Size: 101 MB
Dependencies parsed at: Pending
Created at: almost 6 years ago
Updated at: about 3 years ago
Pushed at: almost 6 years ago
Last synced at: over 2 years ago
Topics: ddr, hls, matrix-multiplication, tutorial, vivado, zynq, zynq-7000