vedranMv/axi_spi_master

IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)

Language: VHDL - Size: 27.3 KB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 7 - Forks: 0