gitlab.com topics: FPGA
spade-lang/spade
A better hardware description language.
Last synced at: 11 days ago - Stars: 70 - Forks: 26
tymonx/pytcl
**PyTCL** allows control **EDA** tools directly from **Python** that use **TCL**.
Last synced at: 12 days ago - Stars: 1 - Forks: 0
xlogic/systemd/flexlm
Using containerized FlexLM license managers as systemd service units for serving FPGA/ASIC EDA software licenses that can be also used in CI/CD flow.
Last synced at: about 1 year ago - Stars: 1 - Forks: 0
xlogic/mono
The mono repository for the xlogic standalone library, services and command line tools.
Last synced at: about 1 year ago - Stars: 1 - Forks: 0
xlogic/tool/questa
Containerized Questa*-Intel® FPGA Edition Software.
Last synced at: about 1 year ago - Stars: 1 - Forks: 0
wojrus-projects/altium-designer/evb/ice40up5k_evb_v1_0
FPGA Lattice iCE40UP5K evaluation board.
Last synced at: almost 2 years ago - Stars: 0 - Forks: 0
wojrus-projects/altium-designer/evb/lcmxo2_evb_v1_0
FPGA Lattice LCMXO2-256ZE evaluation board.
Last synced at: almost 2 years ago - Stars: 0 - Forks: 0
brettops/containers/verible
[Verible](https://github.com/chipsalliance/verible) build container.
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
x653/nand2tetris-fpga
This project is about building Hack on real hardware as proposed in chapter 13 of the course nand2tetris using only FOSS, free and open source hard- and software.
Last synced at: about 2 years ago - Stars: 31 - Forks: 8
lauterbach/jswitch
Lauterbach's JSwitch VHDL IP
Last synced at: about 2 months ago - Stars: 5 - Forks: 0
x653/xv6-riscv-fpga
Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
Last synced at: about 2 years ago - Stars: 5 - Forks: 0
wojrus-projects/altium-designer/lattice_jtag_v1_0
USB 2.0 HS programmer for Lattice FPGA with JTAG or SPI.
Last synced at: almost 2 years ago - Stars: 0 - Forks: 0
suoglu/fpam
Combinational adder and multiplier modules for IEEE 754 single-precision and double-precision floating point format.
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
Lazlo/icestorm-toolchain
Automate building the tools from Project IceStorm
Last synced at: over 2 years ago - Stars: 0 - Forks: 1
gdolle/orangecrab-case
Case for the OrangeCrab FPGA
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
rodrigomelo9/fpgargentina
Relevamiento de grupos de desarrollo, capacidades y casos de uso de la tecnología FPGA en Argentina. https://rodrigomelo9.gitlab.io/fpgargentina/
Last synced at: over 2 years ago - Stars: 4 - Forks: 2
leo-plese/digital-logic/fpga-arduino-digital-logic-semaphore-project
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
suoglu/i2c
Set of simple modules to communicate via I²C Bus.
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
suoglu/pmod
Collection of simple interfaces for Digilent Pmods
Last synced at: about 2 years ago - Stars: 1 - Forks: 0
aadhuniklabs/casp
CASP is developed to assist students, engineers and makers in designing, developing and validating real time embedded system software quickly with little programming effort.
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
rodrigomelo9/pyfpga
A Python package to use FPGA development tools programmatically. It is a mirror of https://github.com/PyFPGA/pyfpga, where the development is done. Documentation: https://pyfpga.github.io/pyfpga
Last synced at: over 2 years ago - Stars: 10 - Forks: 1
busshark/thirdparty/libxsvf
a fork of http://svn.clifford.at/libxsvf/trunk@104
Last synced at: over 2 years ago - Stars: 1 - Forks: 1
leo-plese/digital-logic/digital-logic-sequential-circuits-2-in-vhdl-hardware-description-language-testing-on-fpga-ulx2s-development-board
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
leo-plese/digital-logic/digital-logic-sequential-circuits-1-in-vhdl-hardware-description-language-testing-on-fpga-ulx2s-development-board
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
leo-plese/digital-logic/digital-logic-combinational-circuits-and-registers-in-vhdl-hardware-description-language-testing-on-fpga-ulx2s-development-board
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
leo-plese/digital-logic/digital-logic-circuits-in-vhdl-hardware-description-language-testing-on-fpga-ulx2s-development-board
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
suoglu/uart
Set of simple modules to communicate via UART
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
suoglu/axi-lite-slave
Collection of some simple AXI4-Lite slaves.
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
maCesc/snake
Final project for the MSc course of Laboratory of Advanced Electronics held in 2021 by Prof. Leonardo Ricci at the University of Trento.
Last synced at: over 2 years ago - Stars: 1 - Forks: 0
suoglu/axi-gpio
Custom AXI GPIO core with up to 32 input and 32 output ports
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
suoglu/MCP4725
Interface module for MCP4725 DAC
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
suoglu/verilog-utilty-modules
Collection of utility modules written in Verilog
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
rodrigomelo9/core-comblock
A simple COMmunication BLOCK with well know interfaces in the FPGA side
Last synced at: over 2 years ago - Stars: 8 - Forks: 3
VitalMixofNutrients/vISA
I'm currently working on a hobby project that I will call "vISA", which stands for "Variable Instruction Set Architecture." Because GitLab's Project Description is very limited, just read the README.md instead.
Last synced at: over 2 years ago - Stars: 1 - Forks: 0
suoglu/ir-transreceiver
Encoder and decoder modules for infrared receivers, transmitters and remotes
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
suoglu/sequential-crc-generator
Pair of modules to calculate crc values sequentially
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
lauterbach/jswitch-doc
LaTeX documentation of [JSwitch IP](https://gitlab.com/lauterbach/jswitch)
Last synced at: about 2 months ago - Stars: 1 - Forks: 0
x653/mix-fpga
Implementation of MIX as proposed in "The Art of Computer Programming, Vol. 1" by Donald E. Knuth. Runs on iCE40-fpga using only FOSS Hard- and Software.
Last synced at: over 2 years ago - Stars: 8 - Forks: 1
mlstn12grp/hdl/cordic
CORDIC block meant for FPGA implementation
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
jcorrecher/fifo
A VHDL synthesizable and behavioral FIFO design.
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
cv4497/ie707560_ie705694_dvvsd_p2021
Repositorio grupal DVVSD P2021
Last synced at: over 2 years ago - Stars: 1 - Forks: 0
cv4497/ie707560_dvvsd_p2021
Repositorio Personal DVVSD P2021
Last synced at: over 2 years ago - Stars: 1 - Forks: 0
suoglu/spi
Set of simple modules to communicate via SPI protocol.
Last synced at: about 2 years ago - Stars: 1 - Forks: 0
suoglu/hc-sr04
Verilog interface for HC-SR04 Ultrasonic Ranging Module
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
cmn263/fgdb
A basic FPGA debugging support called fgdb which is based on LegUp’s idea (an HLS-oriented debugging environment that allows to inspect circuitry generated by HLS the same way as GDB does).
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
tymonx/xlogic-toolchain
Toolchain for simulating and building FPGA projects.
Last synced at: 10 months ago - Stars: 1 - Forks: 0
joe_helmick/arty01
Newest version of microprocessor design for Artix-7 100 Digilent Arty board. Includes the migrated Python assembler code as well, and a assembly-language implementation of Conway's Game of Life coded for this design.
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
x653/nand2tetris-13
This project is about building Hack on real hardware as proposed in Chapter 13 of the course nand2tetris using only FOSS, free and open source hard- and software.
Last synced at: over 2 years ago - Stars: 5 - Forks: 1
baioc/s4pu
A stack-based 16-bit CPU written in VHDL (with pt-br docs)
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
tymonx/docker-modelsim
A Docker image with the ModelSim HDL simulator
Last synced at: over 2 years ago - Stars: 4 - Forks: 3
acj0003/zynq_coresight
An Demonstration of FPGA Assisted Software Tracing for ARM CoreSight On Xilinx Zynq-7000 SoC
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
pespi001/ece-484w-lab-3-assigment
Source/Version control task for Lab 3
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
eliotr/RSA_Security_Token
Our bachelor's thesis. A Security token system for Linux PAM using an FPGA. Either utilizing 72-bit or 512-bit RSA cryptography when using Version A and B respectively. Version B is utilizing USB UART communication, while version A is air-gapped.
Last synced at: about 1 month ago - Stars: 0 - Forks: 0
tymonx/logic-toolchain
Wrapper for FPGA toolchain tools
Last synced at: about 1 month ago - Stars: 0 - Forks: 0
leastrobino/acoustic-levitation
Acoustic levitation on SoC FPGA (DE0-Nano-SoC) https://youtu.be/p1Vm4cL4aUA
Last synced at: over 2 years ago - Stars: 1 - Forks: 2
OK2NMZ/thesis-fso
Implementation of a freespace optics bridge.
Last synced at: over 2 years ago - Stars: 1 - Forks: 0