gitlab.com topics: VHDL
dawalters/hdl-block-design
A library to represent and manipulate Hardware Description Language (HDL) block designs in Python https://hdl-block-design.readthedocs.io/en/latest/
Last synced at: about 2 months ago - Stars: 0 - Forks: 1
tymonx/pytcl
**PyTCL** allows control **EDA** tools directly from **Python** that use **TCL**.
Last synced at: 2 months ago - Stars: 1 - Forks: 0
xlogic/tool/questa
Containerized Questa*-Intel® FPGA Edition Software.
Last synced at: over 1 year ago - Stars: 1 - Forks: 0
IEEE-P1076/packages
The source code of all IEEE packages. Development of future opensource.ieee.org/vasg/Packages releases.
Last synced at: about 2 years ago - Stars: 10 - Forks: 2
wlgrw/han-soc-assignment-vhdl-piano
Project templates and materials for the VHDL Piano assignment.
Last synced at: about 2 years ago - Stars: 2 - Forks: 3
_solis/embedded_systems
All VHDL code used for Embedded Systems Lab
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
advanced-applied-electronics/semester-2/vhdl-list-1
Solutions for list with basic tasks with concurrent operations for behavioral simulation.
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
wlgrw/han-soc-examples
VHDL examples for use in D-H-EHE-SOC class
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
progcat/cat16
An 16bit CPU written in VHDL, compile with GHDL.
Last synced at: over 2 years ago - Stars: 1 - Forks: 0
sbannier/machet
A collection of Perl scripts for digital design simulation and FPGA synthesis automation. It supports Verilog, VHDL and mixed language (Verilog + VHDL) designs.
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
leo-plese/digital-logic/digital-logic-sequential-circuits-2-in-vhdl-hardware-description-language-testing-on-fpga-ulx2s-development-board
Last synced at: almost 3 years ago - Stars: 0 - Forks: 0
leo-plese/digital-logic/digital-logic-sequential-circuits-1-in-vhdl-hardware-description-language-testing-on-fpga-ulx2s-development-board
Last synced at: almost 3 years ago - Stars: 0 - Forks: 0
leo-plese/digital-logic/digital-logic-combinational-circuits-and-registers-in-vhdl-hardware-description-language-testing-on-fpga-ulx2s-development-board
Last synced at: almost 3 years ago - Stars: 0 - Forks: 0
leo-plese/digital-logic/digital-logic-circuits-in-vhdl-hardware-description-language-testing-on-fpga-ulx2s-development-board
Last synced at: almost 3 years ago - Stars: 0 - Forks: 0
pt2021_30226_rus_andrei_nicolae/vhdl/calcul
I implemented on a basys3 FPGA board a hardware projects which consists of basic arithmetic operations such as subtraction, addition, multiplier and division
Last synced at: almost 3 years ago - Stars: 0 - Forks: 0
32954/binary-to-7segment
Generic binary to 7-segment display driver
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
jcorrecher/fifo
A VHDL synthesizable and behavioral FIFO design.
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
tymonx/xlogic-toolchain
Toolchain for simulating and building FPGA projects.
Last synced at: 12 months ago - Stars: 1 - Forks: 0
odu-projects/ece_487_fixed
repo for 487 code with a twist: hopefully you will be able to pull from it.
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
baioc/s4pu
A stack-based 16-bit CPU written in VHDL (with pt-br docs)
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
nxfrvt/zegarek
VHDL project for a digital clock with the alarm functionality
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
tymonx/docker-modelsim
A Docker image with the ModelSim HDL simulator
Last synced at: over 2 years ago - Stars: 4 - Forks: 3
WilferCiro/sintel
Webpage: http://wilferciro.gitlab.io/sintel Documentation: https://sintel.readthedocs.io/en/latest/
Last synced at: over 2 years ago - Stars: 3 - Forks: 0
Kcantes/vhdl---aes-model
Projet de chiffrement AES en vhdl, dans le cadre de la formation ISMIN de l'école des Mines de St-Etienne.
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
eliotr/RSA_Security_Token
Our bachelor's thesis. A Security token system for Linux PAM using an FPGA. Either utilizing 72-bit or 512-bit RSA cryptography when using Version A and B respectively. Version B is utilizing USB UART communication, while version A is air-gapped.
Last synced at: 3 months ago - Stars: 0 - Forks: 0
JoacyMS/mi-sistemasdigitais
Projeto do MI - Sistemas Digitais
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
leastrobino/acoustic-levitation
Acoustic levitation on SoC FPGA (DE0-Nano-SoC) https://youtu.be/p1Vm4cL4aUA
Last synced at: over 2 years ago - Stars: 1 - Forks: 2
BlasM/cryptographic-co-processor
Flexible 16-bit cryptographic co-processor written in VHDL and Verilog. From Assigment EE540 DCU Master in Electronic and Computer Engineering
Last synced at: over 2 years ago - Stars: 1 - Forks: 0
Mathe13/sources_1
modela o processador K and S usando vhdl
Last synced at: over 2 years ago - Stars: 0 - Forks: 0
fvb/MIPS_processor
MIPS processor implementation in VHDL which was the project for the computer architecture class at VUB
Last synced at: over 2 years ago - Stars: 1 - Forks: 0
joaomorenorf/Processador
Descrição de hardware do processador para a disciplina Sistemas, Processadores e Periféricos.
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
dylanvanassche/digitale-synthese
DSSS Wireless transmit-receive system in VHDL
Last synced at: about 2 years ago - Stars: 0 - Forks: 0
IEEE-P1076/Interfaces
A list of interface examples for the ongoing work on VHDL Interfaces.
Last synced at: over 2 years ago - Stars: 6 - Forks: 0
bschaefer/DLX-MC
A VHDL description of DLX multicycle implementation
Last synced at: over 2 years ago - Stars: 0 - Forks: 0