yigitbektasgursoy/symmetric_FIR_Verilog_Implementation

A pipelined Symmetric FIR (Finite Impulse Response) filter implementation in Verilog HDL.

Language: Verilog - Size: 1.43 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 1