yuanbo-peng/Combination-Lock

This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.

Language: VHDL - Size: 1020 KB - Last synced at: 17 days ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 3