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GitHub / PyHDI / Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/PyHDI%2FPyverilog
Stars: 575
Forks: 165
Open Issues: 71
License: apache-2.0
Language: Python
Repo Size: 701 KB
Dependencies:
4
Created: over 10 years ago
Updated: about 1 month ago
Last pushed: 10 months ago
Last synced: 25 days ago
Commit Stats
Commits: 301
Authors: 17
Mean commits per author: 17.71
Development Distribution Score: 0.12
More commit stats: https://commits.ecosyste.ms/hosts/GitHub/repositories/PyHDI/Pyverilog
Topics: code-generator, compiler, control-flow-analyzer, dataflow-analyzer, hardware, parser, python, verilog-hdl
Files
Dependencies
- actions/checkout v2 composite
- actions/setup-python v2 composite