GitHub / hell03end / verilog-uart
Simple 8-bit UART realization on Verilog HDL.
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Stars: 32
Forks: 12
Open issues: 5
License: mit
Language: Verilog
Size: 1.36 MB
Dependencies parsed at: Pending
Created at: about 7 years ago
Updated at: over 2 years ago
Pushed at: almost 3 years ago
Last synced at: over 2 years ago
Topics: fpga, hdl, quartus, uart, verilog
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