GitHub / janschiefer / verilog_spi
A simple Verilog SPI master / slave implementation featuring all 4 modes.
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Stars: 15
Forks: 3
Open issues: 0
License: lgpl-2.1
Language: Verilog
Size: 17.6 KB
Dependencies parsed at: Pending
Created at: over 4 years ago
Updated at: over 1 year ago
Pushed at: over 4 years ago
Last synced at: over 1 year ago
Topics: asic, fpga, fpgas, hdl, spi, spi-master, spi-slave, verilog
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