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GitHub / mcquerol / direct-digital-frequency-synthesis-systemverilog

SystemVerilog DDFS project on FPGA. Includes LUT design and sine wave generation.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mcquerol%2Fdirect-digital-frequency-synthesis-systemverilog

Stars: 1
Forks: 0
Open issues: 0

License: mit
Language: SystemVerilog
Size: 509 KB
Dependencies parsed at: Pending

Created at: 9 months ago
Updated at: 4 months ago
Pushed at: 4 months ago
Last synced at: 2 months ago

Topics: ddfs, fpga, lut, pwm, sine-wave, systemverilog, time-base-generation

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