GitHub / mcquerol / direct-digital-frequency-synthesis-systemverilog
SystemVerilog DDFS project on FPGA. Includes LUT design and sine wave generation.
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PURL: pkg:github/mcquerol/direct-digital-frequency-synthesis-systemverilog
Stars: 1
Forks: 0
Open issues: 0
License: mit
Language: SystemVerilog
Size: 509 KB
Dependencies parsed at: Pending
Created at: 11 months ago
Updated at: 6 months ago
Pushed at: 6 months ago
Last synced at: 4 months ago
Topics: ddfs, fpga, lut, pwm, sine-wave, systemverilog, time-base-generation
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