GitHub topics: ddfs
mcquerol/direct-digital-frequency-synthesis-systemverilog
SystemVerilog DDFS project on FPGA. Includes LUT design and sine wave generation.
Language: SystemVerilog - Size: 509 KB - Last synced at: 2 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0
0xastro/RTL_QAM
The project is designed using VHDL to realise the M-QAM modulation.
Language: VHDL - Size: 13.6 MB - Last synced at: about 1 year ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 1
urbanij/DDFS
Direct digital frequency synthesizer in Verilog and VHDL.
Language: VHDL - Size: 9.56 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 2
