GitHub / tharinduSamare / Multicore_processor_verilog_design
This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tharinduSamare%2FMulticore_processor_verilog_design
PURL: pkg:github/tharinduSamare/Multicore_processor_verilog_design
Stars: 1
Forks: 1
Open issues: 0
License: None
Language: Verilog
Size: 7.81 MB
Dependencies parsed at: Pending
Created at: almost 4 years ago
Updated at: about 3 years ago
Pushed at: over 3 years ago
Last synced at: over 2 years ago
Topics: fpga, modelsim, quartus-prime, simulation, verilog
Loading...