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GitHub topics: learning-verilog

hashirshoaeb/Verilog-Codes šŸ“¦

This repository is to help macOS and linux users who have just started learning verilog.

Language: Verilog - Size: 26.3 MB - Last synced at: 3 months ago - Pushed at: almost 6 years ago - Stars: 4 - Forks: 0

mcleber/Verilog_Testbench_Essentials

Creating testbenches in Verilog is an essential practice to verify the functionality of your modules and ensure your design behaves as expected.

Language: Verilog - Size: 66.4 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

mcleber/Verilog_7-Segment_Display_with_DIP_Switches

This project implements a BCD (Binary-Coded Decimal) converter that reads DIP switch input and controls a 7-segment display, showing digits 0ā€“8 or ā€˜Eā€™ for invalid combinations.

Language: Verilog - Size: 816 KB - Last synced at: 5 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

mcleber/Verilog_Traffic_Light_Controller

First steps with the Sipeed Tang Primer 20k FPGA.

Language: Verilog - Size: 1.75 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

Related Keywords
verilog 4 verilog-hdl 3 sipeed-tang-primer 2 sipeed 2 gowin-eda 2 gowin 2 verilog-testbenches 1 testbenches 1 testbench 1 vscode-plugin 1 vscode 1 scansion 1 macos 1 linux-users 1 lab-tasks 1 getting-started 1 assignment 1