GitHub topics: logic-in-memory
BUPTslb/LIMGEN
This project will be the beginning of my research life!
Language: C++ - Size: 29.1 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0
vlsi-nanocomputing/risc-v-lim-architecture
RISC-Vlim is a framework for Logic-in-Memory Architectures based on RI5CY from PULP-Platform
Language: Verilog - Size: 24.4 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0
