GitHub topics: posit-adder
JaHoer/Posit-VHDL-Arithmetic
Simple implementation of a systolic array using posit arithmetic
Language: VHDL - Size: 15.4 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
manish-kj/Posit-HDL-Arithmetic
Universal number Posit HDL Arithmetic Architecture generator
Language: Verilog - Size: 1.03 MB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 42 - Forks: 11
manish-kj/PACoGen
PACoGen: Posit Arithmetic Core Generator
Language: Verilog - Size: 29.4 MB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 47 - Forks: 12