Topic: "control-hazards"
maze1377/pipeline-mips-verilog
A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
Language: Verilog - Size: 229 KB - Last synced at: 25 days ago - Pushed at: 3 months ago - Stars: 43 - Forks: 8
Mahekkumar-Varasada/5-Stage-MIPS-Pipelined-with-Hazard-Mitigation
The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.
Language: Verilog - Size: 75.2 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0
sebastian-wardzinski/computer-architecture
ECE552: Computer Architecture — Fall 2020.
Language: C - Size: 9.66 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 1
NuttySalmon/MIPS-Processor-FPGA
Pipline MIPS processor implementation on Basys 3 with hazard handling and memory mapped IO.
Language: Verilog - Size: 5.07 MB - Last synced at: 8 months ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0
