GitHub / ben-marshall / verilog-probe
A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ben-marshall%2Fverilog-probe
Stars: 11
Forks: 3
Open issues: 1
License: mit
Language: Python
Size: 203 KB
Dependencies parsed at: Pending
Created at: over 7 years ago
Updated at: 29 days ago
Pushed at: over 7 years ago
Last synced at: 18 days ago
Topics: debugger, fpga, hdl, probe, python3, uart, verilog
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