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GitHub topics: chipdesign

efabless/sky130_klayout_pdk

Skywaters 130nm Klayout PDK

Language: Python - Size: 88.8 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 21 - Forks: 13

ChrisShakkour/RV32I-MAF-project

Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF

Language: SystemVerilog - Size: 10.4 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 6 - Forks: 1

Related Keywords
chipdesign 2 pdk 1 skywaters 1 assembly 1 core 1 isa 1 pipline 1 risc-v 1 riscv 1 rtl 1 systemverilog 1 vlsi 1 vlsi-design 1