GitHub topics: cva6
sifferman/labs-with-cva6
Advanced Architecture Labs with CVA6
Language: SystemVerilog - Size: 311 KB - Last synced at: 2 days ago - Pushed at: over 1 year ago - Stars: 59 - Forks: 26
adamhlt/LiteX-CVA6
LiteX CVA6 - Fixed integration of the CPU into LiteX SoC generator
Language: C++ - Size: 13.5 MB - Last synced at: 1 day ago - Pushed at: almost 2 years ago - Stars: 5 - Forks: 2
ThalesGroup/cva6-baremetal-bsp
Provides baremetal support for the CVA6 COREV APU on GENESYS2
Language: C - Size: 499 KB - Last synced at: about 2 months ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 4
ThalesGroup/meta-openhw
Yocto layer for OpenHWGroup
Language: Shell - Size: 124 KB - Last synced at: about 1 month ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 4
jimaandro/JTAG_TO_AXI
These scripts are used in a Vivado project, to implement jtag to axi transactions. The general project is to run baremetal cpp code on Ariane RISC-V core
Language: Tcl - Size: 16.4 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
val-gfr/thales-cva6-contest
Our work as students (Team Breizh Hat) for the national CVA6 softcore hackathon organized by Thales Group
Size: 22.2 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
LCAI-TIHU/HW
LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals.
Language: Verilog - Size: 47 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 19 - Forks: 8
