GitHub topics: phase-locked-loop
mryndzionek/dpll_design_notes
Digital PLL design notes
Size: 753 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
Ernane-AAC/Arduino-PLL
This repository shows how to implement a simple PLL and a Frequency Meter using Arduino Uno.
Language: HTML - Size: 6.32 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
manili/VSDBabySoC
VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
Language: Verilog - Size: 11.5 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 27 - Forks: 10
DericAugusto/ISN2022_InfTransmission
Material from the course of Information Transmission at ENSEM - Université de Lorraine.
Language: MATLAB - Size: 101 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
antonysigma/femptosecond-pulse-trigger-pcb
Decoding 400 picosecond pulse train to 15 MHz clock signal
Language: GLSL - Size: 412 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
