GitHub topics: standard-cell
furrtek/SiliconRE
Traces, schematics, and general infos about custom chips reverse-engineered from silicon
Language: Verilog - Size: 485 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 175 - Forks: 14
rodrigowue/pyLEX
pyLEX - SPICE STD-CELL ARCS EXTRACTOR (but in Python)
Language: Python - Size: 14.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0
furrtek/ASICRE
Logic cell info for gate array and standard cell ASIC reverse-engineering
Size: 6.26 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 5 - Forks: 0