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GitHub topics: jala

ndyashas/Salaga-RV

Simple RISC-V CPUs running a baremental ray-tracer program.

Language: Verilog - Size: 884 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0

Related Keywords
5-stage-pipeline 1 5-stages-pipeline 1 baremetal 1 baremetal-programming 1 cpu 1 cpu-simulation 1 eka 1 jala 1 risc-v 1 riscv 1 rv32i 1 single-cycle 1 verilator 1 verilog 1