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GitHub topics: arraymultiplier

RoshanK789/Day-7-task

day 7 task

Language: JavaScript - Size: 1000 Bytes - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

sumitarohit/Array_Multiplier_project

This is a 4*4 Array_Multiplier_project using Verilog HDL. This is successfully implemented on FPGA board.

Language: Tcl - Size: 179 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Related Keywords
arraymultiplier 2 filter 1 javascript 1 map 1 reduce 1 xmlhttprequest 1 fpga 1 fpga-board 1 verilog-code 1 verilog-hdl 1 verilog-project 1