Layheng-Hok/Digital-Piano

Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100

Language: Verilog - Size: 9.97 MB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 2 - Forks: 1

OctCarp/SUSTech_CS207-DD_2022f_Project-a-real-car

(Verilog+FPGA EGO1) (140/100) A real car: our project of CS207 2022 Fall: Digital Logic Design, SUSTech. Taught by Prof. James YU @James-Yu.

Language: Verilog - Size: 54.4 MB - Last synced at: 21 days ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0

LunaQu4kez/CS207_23F_Project_GenshinKitchen

2023 Fall CS207 Digital Design Course Project with 120/100 (Full Score)

Language: VHDL - Size: 88.6 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 0

Certseeds/CS207_Digital_Design 📦

SUSTech CS207 Digital Design 2018Fall Materials.

Language: Verilog - Size: 15.1 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 5 - Forks: 0

arvillion/puzzle

A simple jigsaw puzzle game on FPGA, the final project of SUSTech CS207 2021f

Language: VHDL - Size: 56.9 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

afridimatin/CS207

Language: C++ - Size: 14.6 KB - Last synced at: 12 months ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0