GitHub topics: myhdl
mbuesch/crcgen
Generator for CRC HDL code (VHDL, Verilog, MyHDL)
Language: Python - Size: 113 KB - Last synced at: 5 days ago - Pushed at: over 1 year ago - Stars: 37 - Forks: 9
jmgc/myhdl-numeric
Myhdl fork that includes support for multiple entities (MEP110) and fixed point functionality (MEP 111) on VHDL. See myhdl/numeric dir under the numeric branch, and the Cordic example (example/cordic/Cordic.ipynb).
Language: Python - Size: 13.8 MB - Last synced at: 2 months ago - Pushed at: 3 months ago - Stars: 4 - Forks: 1
AngelTerrones/Basic-verilog-project
Basic example of a 4-bit ALU, cosimulated using myHDL. Provides a makefile for synthesis (using Xilinx ISE)
Language: Shell - Size: 8.79 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0
AzeezEbrahim/myHDL-project
This is a simple CPU using myHDL package.
Language: Python - Size: 2.37 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0
tomtor/HDL-deflate
FPGA implementation of deflate (de)compress RFC 1950/1951
Language: Verilog - Size: 476 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 34 - Forks: 1
davidbrochart/pyclk
Python implementation of a Hardware Description Language (HDL)
Language: Python - Size: 90.8 KB - Last synced at: 3 months ago - Pushed at: over 6 years ago - Stars: 5 - Forks: 0
world-of-open-source/MyHDL-Collections
Your one-stop shop for all fpga programs- in your favourite language-->Python
Language: Verilog - Size: 13.7 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 0
