Topic: "fault-simulation"
litmuschaos/litmus
Litmus helps SREs and developers practice chaos engineering in a Cloud-native way. Chaos experiments are published at the ChaosHub (https://hub.litmuschaos.io). Community notes is at https://hackmd.io/a4Zu_sH4TZGeih-xCimi3Q
Language: Go - Size: 137 MB - Last synced at: 6 days ago - Pushed at: 10 days ago - Stars: 4,687 - Forks: 724
AUCOHL/Fault
A complete open-source design-for-testing (DFT) Solution
Language: Swift - Size: 4.29 MB - Last synced at: 25 days ago - Pushed at: 7 months ago - Stars: 147 - Forks: 32
NTU-LaDS-II/FAN_ATPG
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
Language: Verilog - Size: 10.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 51 - Forks: 11
amamory-verification/hw-formal-verif
Hardware Formal Verification
Language: Verilog - Size: 3.74 MB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 10 - Forks: 3
kalexio/fault-simulator
Simple fault simulator
Language: C - Size: 99.6 KB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 5 - Forks: 0
MakisChristou/ParallelCircuitSimulator 📦
A serial and parallel logic fault simulator on gate level netlists.
Language: TeX - Size: 15.4 MB - Last synced at: 4 days ago - Pushed at: almost 5 years ago - Stars: 5 - Forks: 1
Mrcuve0/TFT-RI5CY-Assignment
Source files and documentation for the final assignment of the "Testing and Fault Tolerance" course.
Language: Verilog - Size: 31.3 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 2
cad-polito-it/r4ves
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
Language: Verilog - Size: 4.07 MB - Last synced at: about 1 month ago - Pushed at: 12 months ago - Stars: 1 - Forks: 1
AndreasKaratzas/circuit-simulation
This is a Combinational Circuit Logic Simulation Tool. There is a C++ version and a C version.
Language: C++ - Size: 442 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 1
kanndil/PODEM-ATPG
Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG).
Language: Python - Size: 112 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
celine-hsieh/VLSI-Testing-LAB-1
Fault Simulation | Parallel Fault Simulation | Deductive fault Simulation | Test Coverage
Language: Verilog - Size: 10.1 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
ucchino/caliban
A fault simulator that adopts an algorithm called "GODFATHER" created by Pier Paolo Ucchino
Language: C - Size: 135 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0
