Topic: "rtl-coding"
JAYRAM711/100-DAYS-OF-RTL
This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools
Language: Verilog - Size: 40 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 12 - Forks: 1
Nidhinchandran47/my_rtl_code
Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog
Language: Verilog - Size: 1.67 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 10 - Forks: 1
OrsuVenkataKrishnaiah1235/RTL-Coding
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
Language: Verilog - Size: 8.66 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 6 - Forks: 3
Kethasriramya2912/Verilog-RTL-Coding
"Mastering RTL-Coding : From Fundamentals to Advanced Programming Techniques using Verilog,System Verilog and UVM"
Language: Verilog - Size: 64.5 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 3 - Forks: 0
Venkaraddi7/Elevator_Controller
To implement the elevator controller, we used Verilog as HDL. The focus of our project was the implementation and verification of a controller for a basic elevator functionality. We also proposed a methodology that utilizes the SCAN algorithm to enhance the efficiency and reliability of the controller.
Language: Verilog - Size: 1.58 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
