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GitHub / SystemRDL / PeakRDL

Control and status register code generator toolchain

JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SystemRDL%2FPeakRDL

Stars: 74
Forks: 16
Open Issues: 5

License: gpl-3.0
Language: Python
Repo Size: 125 KB
Dependencies: 16

Created: about 4 years ago
Updated: 26 days ago
Last pushed: 7 months ago
Last synced: 18 days ago

Commit Stats

Commits: 43
Authors: 2
Mean commits per author: 21.5
Development Distribution Score: 0.023
More commit stats: https://commits.ecosyste.ms/hosts/GitHub/repositories/SystemRDL/PeakRDL

Topics: amba, apb, asic, axi, command-line-tool, csr, eda, fpga, hardware-description-language, register-descriptions, registers, systemrdl-compiler, systemverilog, uvm, uvm-register-model, verilog

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    Dependencies