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GitHub topics: clock-tree-synthesis

Vishwajeetsinh-K/RTL2GDS_demux

An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full 1×8 demux for 8-bit data — all the way from Verilog to GDSII.

Size: 4.88 KB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 0 - Forks: 0

KAMATHAM19/RTL-to-GDSII-ASIC-design-of-Counter

The objective is to take a simple counter design from the RTL (Register Transfer Level) stage to the GDSII format using Cadence tools with a 90nm Process Design Kit (PDK).. The tools used in this process include Xcelium for simulation and coverage analysis, Genus for synthesis, Innovus for physical design, and Pegasus/PVS for physical verification.

Language: Tcl - Size: 56.6 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Related Keywords
clock-tree-synthesis 2 rtl 2 synthesis 2 sta 1 simulation 1 routing 1 rc-extraction 1 powerplan 1 placement 1 physical-verification 1 gdsii 1 floorplan 1 coverage-analysis 1 vlsi 1 verilog 1 rtl-to-gdsii 1 icc2 1 hdl 1 hardware-design 1 floorplanning 1 digital-design 1 design-compiler 1 demux 1 asic 1