limerainne/Dockerize-EDA

[WIP] Dockerize Synopsys/Cadence EDA tools

Language: Dockerfile - Size: 25.4 KB - Last synced at: about 1 month ago - Pushed at: about 6 years ago - Stars: 85 - Forks: 24

foss-for-synopsys-dwc-arc-processors/embarc_osp

embARC Open Software Platform (OSP) - An embedded software distribution for IoT and other embedded applications for ARC

Language: C - Size: 171 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 67 - Forks: 61

kaushalmodi/custom_uvm_report_server

Customized UVM Report Server

Language: SystemVerilog - Size: 424 KB - Last synced at: 3 days ago - Pushed at: over 5 years ago - Stars: 40 - Forks: 10

minhoolee/Synopsys-Project-2017

A deep learning based bioinformatics project on epigenetics in Type 2 Diabetes.

Language: Jupyter Notebook - Size: 2.68 MB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 16 - Forks: 4

mperov/fixSegfaultVCS

There is segmentation fault of VCS which should be fixed.

Language: Python - Size: 35.2 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 14 - Forks: 2

iDoka/mastering-fpgasic-book

:book: Mastering FPGASIC Book

Size: 1.95 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 14 - Forks: 4

erihsu/tf-parser

Technology file parser in Rust

Language: Rust - Size: 94.7 KB - Last synced at: 25 days ago - Pushed at: about 4 years ago - Stars: 12 - Forks: 2

Juanx65/RISC-V

Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.

Language: Verilog - Size: 115 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 10 - Forks: 4

gabrielganzer/RTL-PowerOptimization

Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

Language: Verilog - Size: 811 KB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 9 - Forks: 1

lnishan/Curriculum-Vitae

:star2: Jasmine "lnishan" Chen's Curriculum Vitae (CV) in Markdown

Language: CSS - Size: 1.02 MB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 9 - Forks: 0

kkiningh/synthesis-example

Example of a full DC synthesis script for a simple design

Language: Tcl - Size: 12.7 KB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 7 - Forks: 4

gabrielganzer/DLX-Microprocessor

Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.

Language: Verilog - Size: 88.7 MB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 6 - Forks: 0

parthpower/DCC_Basic

Typical project for Synopsys DC Compiler

Language: Tcl - Size: 17.6 KB - Last synced at: about 2 months ago - Pushed at: almost 7 years ago - Stars: 6 - Forks: 2

jenkinsci/synopsys-security-scan-plugin Fork of synopsys-sig/synopsys-security-scan-plugin

Synopsys Security Plugin provides functionality for performing Security Scan with Black Duck, Coverity and Polaris.

Language: Java - Size: 1.66 MB - Last synced at: 4 months ago - Pushed at: 5 months ago - Stars: 5 - Forks: 0

iDoka/iDoka.github.io

iDoka's web page on Github

Size: 195 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 1

thaljef/blackduck-detect-bash-completion

Command completion for Synopsys (Black Duck) Detect commands

Language: Shell - Size: 23.4 KB - Last synced at: 15 days ago - Pushed at: 24 days ago - Stars: 3 - Forks: 1

abdelazeem201/APB-I2S

I2S (Inter-IC Sound) interface module with APB (Advanced Peripheral Bus) interface signals. It has control logic for writing and reading data to/from a 4x32-bit FIFO and generates clock (sck), word select (ws), and serial data (sd) signals for I2S transmission.

Language: Verilog - Size: 72.3 KB - Last synced at: about 2 months ago - Pushed at: 7 months ago - Stars: 3 - Forks: 0

Vincenzo-Petrolo/DLX-RISC-microprocessor

DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino

Language: Verilog - Size: 147 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 2

rabieifk/Synthesis-and-TCL-Scripting

Exploring Synopsys(R) synthesis tools

Language: Verilog - Size: 43.9 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 2

andrea4g/low_power_contest

Master degree project for Synthesis and Optimization of Digital Systems

Language: Verilog - Size: 85.5 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 1

kkiningh/asic-design

A small collection of tutorials and tools for ASIC design.

Language: SystemVerilog - Size: 60.5 KB - Last synced at: almost 2 years ago - Pushed at: about 8 years ago - Stars: 3 - Forks: 0

mdvico/WaveformViewer

Waveform viewer for Synopsys CustomCompiler, text table format, simulation data

Language: Python - Size: 18.6 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 2 - Forks: 1

Nived151/FET-DigitalLib

A Collection of Digital Library of both Schematic & Layout using 70nm FET

Language: Tcl - Size: 617 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 2

xevozen/JK-flipflop-CMOS-using-Synopsys

Designing JK Flip-Flop CMOS using Synopsys Custom Compiler.

Size: 622 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

kholoud0/ASIC-Implementauion-of-CV32E40S-RISC-V-core-

This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).

Language: SystemVerilog - Size: 84.5 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

Luca-Dalmasso/LL_contest

Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT

Language: Verilog - Size: 139 KB - Last synced at: 9 months ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 1

joolzg/mold Fork of rui314/mold

Mold: A Modern Linker 🦠 ARCV2 Support, Linker Script support is the aim for embedded projects

Language: C++ - Size: 24 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

Hstrauss1/8by8-Shape-Transistor-Classifier

8×8 Shape Classifier at the transistor level! Validated through logic design

Size: 503 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

panastasiadis/soc-verification-with-cad-tools

This repository is about the main project of the course "VLSI System Design". This course is a part of the undergraduate studies of University of Thessally - ECE Department located in Volos, Greece.

Language: Verilog - Size: 8.72 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

alessblaze/gcc Fork of gcc-mirror/gcc

Compilers for CAD tools

Size: 3.15 GB - Last synced at: 7 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Pritam-Sethuraman/USB-Core

Language: VHDL - Size: 200 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Project-Saksham/Documents

Size: 712 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

claziss/csibe Fork of szeged/csibe

CSiBE

Language: C - Size: 20.2 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 1

shenxianpeng/ansible-role-polaris

Ansible Role: Polaris - Installs and configures Polaris CLI

Size: 11.7 KB - Last synced at: 11 days ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0