GitHub topics: risc-v32
Alessandro-Salerno/ezld
Tiny, simple, and portable ELF linker
Language: C - Size: 537 KB - Last synced at: 8 days ago - Pushed at: 9 days ago - Stars: 3 - Forks: 0
polarfire-soc/polarfire-soc-discovery-kit-reference-design
PolarFire SoC Discovery Kit Product Page
Language: Tcl - Size: 2.43 MB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 9 - Forks: 5
abdelazeem201/RV32E201X
RV32E201X is a 5-stage pipelined 32-bit RISC-V processor core.
Language: Verilog - Size: 20.5 MB - Last synced at: 15 days ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 3
ErickOF/MP6134-FunctionalVerification-Project
Funtional verification for darkriscv.
Language: SystemVerilog - Size: 392 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0
meloncruuush/RISC-V-Circular-Linked-List
Implementation of a circular linked list in RISC-V. Developed with Ripes (v.2.2.6) for a 32 bit 5 stages processor.
Language: Assembly - Size: 22.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
