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GitHub topics: graycode

Madhu-Krishnan-A-P/binary-gray-converter

SystemVerilog implementation of a Binary to Gray Code Converter in both structural and behavioral styles. Includes a simple testbench for verification. Useful for digital design learners and FPGA developers.

Language: SystemVerilog - Size: 222 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 0 - Forks: 0

hdl-util/gray-code

Generate a gray code of arbitrary width in SystemVerilog

Language: SystemVerilog - Size: 9.77 KB - Last synced at: 10 days ago - Pushed at: almost 5 years ago - Stars: 4 - Forks: 1

sayeekumar332/PROCESSOR-MICROARCHITECTURE

This is a repository exclusively created for providing open source verilog codes for various processor microarchitectures and various programming language based codes for research purpose

Language: Verilog - Size: 251 KB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

Iman9mo/logic-circuit

convert gray code to bcd code and vice versa using verilog

Language: Verilog - Size: 1.95 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Related Keywords
graycode 4 verilog 3 bcd 2 systemverilog 2 gray 2 multithreading 1 processor 1 microprogrammed 1 rtl 1 microarchitecture 1 thread 1 master-slave 1 java 1 instruction 1 hardwired 1 flip-flops 1 excess-3 1 decoder 1 cpu 1 logic-circuit 1 gray-code 1 fpga 1 coding 1 code 1 xilinxvivado 1 xilinx-vivado 1 vlsi 1 vivado 1 testbench 1 system-verilog 1 digital-system 1 digital-design 1 converter 1 binary-gray-converter 1 binary 1