GitHub topics: hardware-synthesis
gussmith23/lakeroad
FPGA synthesis tool powered by program synthesis
Language: Racket - Size: 4.36 MB - Last synced at: 6 days ago - Pushed at: 27 days ago - Stars: 49 - Forks: 8
nicolasbenatti/hw-convolutional-encoder
Digital Logic Design project at Politecnico di Milano
Language: VHDL - Size: 1.3 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0
rbostandoust/CapNet-Accelerator
Hardware accelerator for Capsule Neural Networks
Language: Python - Size: 1.75 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
tongplw/HW-Syn-Lab
⚙Hardware Synthesis Laboratory Using Verilog
Language: Verilog - Size: 16.2 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 34 - Forks: 9
benallard/nextpnr-turingtumble
A nextpnr arch definition for the TuringTumble board game.
Language: Verilog - Size: 24.4 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
natTP/2110363-hw-syn-lab
Code written during 2110363 HW SYN LAB I course, Academic Year 2021, Chulalongkorn University.
Language: Verilog - Size: 23.3 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
InvincibleJuggernaut/ALU
Design for 4 bit ALU with essential logical and arithmetic modules.
Language: Verilog - Size: 1.11 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
