GitHub topics: nexys-video
eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Language: Tcl - Size: 36.1 MB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 933 - Forks: 209
UCL-Proton-Beam-Therapy/VHDL_vivado_basic
A guide on how to write basic FPGA programming in VHDL and its implementation. This targeted the one who has no experience with Vivado.
Language: Tcl - Size: 104 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0
ZipCPU/videozip
A ZipCPU SoC for the Nexys Video board supporting video functionality
Language: Verilog - Size: 9.34 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 16 - Forks: 1
Joel-Dandin/vivado-risc-v Fork of eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Language: Tcl - Size: 36.1 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 2
trash4299/Sudoku-Solver-Nexys 📦
Sudoku Solver using the Nexys Video board
Language: Coq - Size: 285 KB - Last synced at: about 1 year ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0
AmirhosseinR/VeeRwolf
VeeRwolf (a platform for the VeeR family of RISC-V cores) for Nexys Video Board: https://github.com/chipsalliance/VeeRwolf
Language: Verilog - Size: 1.54 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
suoglu/AXI-lite-slave
Slaves for AXI-lite interface
Language: Tcl - Size: 188 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 1
