vhdl-verilog | Topic | Ecosyste.ms: Repos

Topic: "vhdl-verilog"

Multimedia-Processing/Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Language: Verilog - Size: 181 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 6 - Forks: 2

Hithaishisr/Router-1x3

A 1x3 packet router implemented in Verilog HDL, synthesized using Xilinx ISE with complete RTL and testbench support.

Language: Verilog - Size: 21.5 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

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