GitHub topics: verilog-code-examples
muhammadtalhasami/RV32I_Single_Cycle
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
Language: Verilog - Size: 168 KB - Last synced at: about 1 month ago - Pushed at: 10 months ago - Stars: 3 - Forks: 0
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risc-v-pipeline
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