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GitHub topics: risc-v-processor

Pathfinder1996/computer-architecture-homework

1131 NTU CSIE Computer Architecture Homework

Language: Verilog - Size: 2.07 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0

akira2963753/RISC-V-CPU-on-FPGA

32-bit RISC-V CPU Based on RV32I including Forwarding, Hazard, Flush and Brach Predictor.

Language: Verilog - Size: 121 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 2 - Forks: 0

muhammadtalhasami/RV32I_Single_Cycle

This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

Language: Verilog - Size: 168 KB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0

Related Keywords
risc-v-processor 3 risc-v 2 risc-v-assembly 2 verilog 2 vhdl 1 verilog-codes 1 verilog-code-examples 1 verilator 1 system-verilog-codes 1 system-verilog 1 single-cycle-processor-gtkwave-image 1 single-cycle-processor 1 rv32i-processor 1 rv32i 1 risc-v-processor-images 1 risc-v-pipeline 1 pipeline-processor 1 muhammadtalhasami-github- 1 hardware-designs 1 gtkwave 1 fetch-stage-pipeline 1 riscv32 1 riscv-cpu 1 riscv 1