GitHub topics: system-verilog-codes
aumkarrb/FPGA_Prototyping_SystemVerilog-Verilog
Solved SystemVerilog/Verilog Examples from Pong-P-Chu book
Language: Verilog - Size: 16.5 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 0
muhammadtalhasami/RV32I_Single_Cycle
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
Language: Verilog - Size: 168 KB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0