GitHub topics: single-cycle-processor-gtkwave-image
muhammadtalhasami/RV32I_Single_Cycle
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
Language: Verilog - Size: 168 KB - Last synced at: about 1 month ago - Pushed at: 10 months ago - Stars: 3 - Forks: 0

codingwthisa/Procesador-Monociclo-RISCV
Implementación del procesador monociclo RISC-V en System Verilog.
Language: SystemVerilog - Size: 31.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
